Hardware design of video surveillance system based

Hardware design of video surveillance system based on DM642

this paper introduces the working process of embedded video surveillance system. In this paper, the special multimedia processing chip TMS320DM642 newly launched by TT Company is used as the main control chip to realize the function of simultaneously collecting 4 channels of audio and video for local playback, which effectively reduces the cost and improves the utilization of the system. The system is mainly composed of DM642 module, storage module, video module, audio module and power module. These modules are introduced one by one in this paper

keyword video surveillance TMS320DM642 I2C bus

introduction

with the improvement of people's living standards and the growth of the demand for security in the working and living environment, video surveillance system has developed rapidly in recent years. The traditional video monitoring system based on PC has many shortcomings, such as inconvenient to install and carry, and can not be used in harsh environments, which requires the emergence of a new video monitoring system. With the rapid development of VLSI and embedded software and hardware technology in recent years, especially the emergence of embedded chips such as DSP and PowerPC, the application of embedded processor in video monitoring system not only overcomes some shortcomings of the above PC based system, but also its strong functions, rich peripheral interfaces and high programmability make it easier to realize the hardware and software of video monitoring. It is precisely because of the increasingly high cost performance, coupled with the unique advantages of small size and low cost, that embedded chips have gradually gained a place in the field of video surveillance

1 system overview

the general video monitoring system designed in this paper adopts the special multimedia chip TMS320DM642 (DM642 for short) produced by TI company in 2002 as the processor, which can realize the simultaneous acquisition of four channels of audio and video, and support complex audio and video compression algorithms (such as MPEG4 standard), and can carry out the acquisition, playback and storage of audio and video 24 hours a day

the working process of the system is as follows: after the system is powered on or reset, load the program from flash to complete the experiment on chip 5, with a resolution of 1/± 300000 F The initialization of S (the whole process resolution remains unchanged) and the configuration of peripheral hardware, and then the image acquisition begins. DM642 controls other chips in the system through I2C port. The simulated video signal collected from the camera is converted into digital video signal through video decoder and sent to the video channel (VP port) of DM642; The synchronously collected analog audio signal is sent to the DM642 audio channel (mcasp port) after analog/digital conversion of the audio codec. DM642 compresses the received digital video signals and digital audio signals with MP2 to view the business license and relevant national qualifications EG4 standard coding, and then stores the data in file format to the local hard disk through the ATA interface extended by DM642 for future calls. The system is mainly composed of the following modules: DM642 module, storage module, video and audio module, power module, etc. the system structure is shown in Figure 1

2 DM642 module

dm642 is based on C64x kernel, and many peripheral devices and interfaces are added on it, so it is more widely and simply used in practical projects. The system uses a 50MHz crystal oscillator as the external clock input of DSPs, and generates a 600MHz working frequency after 12 times the frequency of the internal phase-locked loop. DM642 adopts two-level cache structure (L1 and L2), which greatly improves the running performance of the program. The on-chip 64 bit EMIF (externalmemory interface) interface can be seamlessly connected with SDRAM, flash and other memory devices, which greatly facilitates the movement of a large amount of data. More importantly, as a special video processing chip, DM642 includes three special video ports (VP0 ~ VP2) for receiving and processing video and audio data, which improves the performance of the whole system. In addition, the EMAC port of the DM642 and the ATA port extended from the emtf port also provide a storage channel for the massive data generated after processing

3 video and audio module

in the design, VP0 of DM642, a channel of VPL, and a and B channels of VP2 are configured as video acquisition mode, which can collect 4 video signals at the same time. If local playback is required, set channel a of VP0 port to playback mode, and at this time, up to 3 video signals can be collected. In addition, the B channels of VP0 and VPL are configured as mcasp functions for audio processing. The data between DM642 and video and audio codec chips are transmitted through these special ports, but the control of these chips is realized through I2C bus

3.1 the video input part

uses an analog camera to collect video data. It needs to use a video decoding chip to digitize the collected analog data, and then send it to the video port of DM642 for processing. Here, four pieces of tvp150a produced by Ti public are selected, and the connection with DM642 is shown in Figure 2 (only the connection diagram of one chip is given)

in Figure 2, the yout port of tvp5150a is directly connected with the VPO port of DM642 for data transmission. Dot matrix clock line and VP0 of VP port on DM642_ CLK is connected to clock signal for data transmission. DM642 reads and writes the internal register of tvp5150a through I2C bus to control the chip

3.2 video output part

VP0 a channel is used for video playback in the design. When playing back the collected data, it is necessary to convert the digital video signal into analog signal before playing it on the monitor. This conversion is completed by saa712l produced by Philips company. The circuit connection diagram of the video playback part is shown in Figure 3

in Figure 3, the VP0 port of DM642 outputs digital video signals in BT.656 format to the MP port of saa7121, and Y signals, CB and CT signals are separated through the internal data management module of saa712l chip; Then it is sent to the corresponding a/D conversion module in the chip to convert the digital signal into analog video signal; Finally, it is output by CVBS (composite video signal) or Y, C (s-terminal signal) pins. The clock signal LLC of saa712l is 27 MHz, which is provided by vp0clkl of DM642, while vp0clkl of DM642 is from SCLK pin of tvp5150a, which makes the video acquisition and playback meet the synchronization requirements. DM642 configures 48 registers in saa7121 chip through I2C interface to realize the control of the chip

3.3 audio module

the audio codec chip in the system adopts tlv320aic23b chip of TI company, which includes three interfaces: ① serial control interface, which is connected with I2C interface of DM642; ② The analog audio interface is used to receive the analog audio signal from micin/linein, or output the analog audio signal of line-out; ③ Digital audio interface for data transmission with mcasp port of DM642. Tlv320aic23b receives the audio signal from the analog audio interface (micin/linein), performs a/D conversion, transmits the digital audio signal to the mcasp of DM642 through the digital interface for processing, and then saves it to the local hard disk together with the processed video signal. When playback is required, the digital audio data without coding processing is transmitted back to tlv320aic23b by mcasp, which is output from the analog audio interface (lineout) after D/a conversion. DM642 configures and controls the chip through I2C interface. The connection mode of four tlv320aic23b chips on I2C bus is the same as that of tvp5150a

3.4 I2C bus

this system uses four video decoding chips, four audio codec chips and one video encoding chip, each chip provides two slave addresses, so the system can complete the control of four chips of the same model only by using two sets of I2C buses. The DM642 chip itself only provides an I2C bus interface, so it is also necessary to use a 2-out-of-1 switcher sn74cbt3257 to switch to Jigang or Sinosteel, which has less environmental pressure, so that the DM642 can only receive one group of two I2C buses at a time. The connection diagram is shown in Figure 4

4 memory module

dm642, which can greatly extend its application life, and the address mapping in memory is divided into four independently addressable spaces ce[3:o], each accounting for 256MB from address 0x. These four addressing spaces can be configured according to the characteristics of the data width of the chip selected in the design. Among them, ce0 space is configured with 64 bit width, which is only used for SDRAM memory mapping; The cel space is configured with 8-bit width for the mapping of flash and UART; CE2 space is configured with 16 bit width for mapping ATA registers; Ce3 is not used in this design and can be used as an expansion sub card in the future. The expansion diagram is shown in Figure 5

5 power module

in the process of system design, the power module plays an important role. It consists of two parts: power supply circuit and power monitoring circuit

5.1 power supply circuit

the whole circuit board is powered by +5 V voltage, which can be introduced from the outside or from the extended PCI interface. DM642 chip requires two independent voltages: CPU core voltage CVDD (+l.4v) and peripheral I/O voltage dvdd (+3.3v). These two voltages need to be carried out in strict order when supplying power, that is, CVDD should be powered on earlier than dvdd, at least not later than dvdd. In the design, two power chips tps543lo designed by TI company for the application of high-performance DSP, FPGA, ASIC and microprocessor are used to provide CVDD and dvdd voltage to DM642 respectively. Connect the pwrgd pin of tps54310 (1) to the SS/EN pin of tps54310 (2) on the circuit connection. When the output voltage of (1) is higher than 1.2 V, the chip (2) starts to work; When this value reaches a stable +l.4 V, the pwrgd pin outputs a high level to the SS/EN pin of the chip (2). This ensures that the power on time of the CPU core is earlier than that of the I/O, as shown in Figure 6 (a)

5.2 power monitoring circuit

in order to ensure that the DM642 chip will not produce an uncontrolled state when the power supply does not reach the required level, and allow each chip in the system to adjust the working state by resetting at any time, it is necessary to add a power monitoring circuit to the system, as shown in Figure 6 (b). This circuit can ensure that the DSP is always in the reset state before the CVDD and dvdd reach the required level during the power on process of the system. Tpss82333 chip produced by TI company is selected, and its fixed reset signal time is up to 200 ms, which can meet the reset requirements of all chips in the system. The chip is equipped with a watchdog circuit, which receives the timing signal from the CPU through the WDI pin to avoid the system program flying

conclusion

dm642 has high-speed processing ability and excellent external interface ability, which makes its designed products superior to special video codec chips in image quality, hardware cost, flexibility and product update. In terms of data storage, the system can not only choose the local storage mode, but also use the EMAC interface in DM642 to save a large amount of processed data to the server through the network, or save the data to the hard disk in the host through the PCI port. This easy scalability enables users to have more choices in the actual use process